1. Field of the Invention
The present invention relates to power management circuits. More particularly, the present invention relates to a circuit and method for dynamic in-rush current control in a power management circuit.
2. Background Information
Conventional computing systems (including, but not limited, to personal computers, cellular phones, personal digital assistants, media players, digital cameras, and the like) include power control features. Power control features are used to reduce dynamic and static power consumption of a system to increase the battery life and to reduce energy consumption of the system. Such functionality is particularly valuable in mobile devices. Dynamic power is consumed by all components of a system during state switching of internal electronic circuits (while the device is in active operation), whereas static power is consumed due to the leakage currents of electronic devices when no switching is occurring.
In a conventional low-power memory device, sleep (power minimization) transistors are used to cut off power supplies to logic blocks of the memory device when the device is operating in standby mode. In such an approach, sleep transistors are used between a global supply rail (e.g., grounded supply in case of N-channel sleep transistors) and a local power supply rail of a logic block or circuit block of the memory device. During a sleep mode of the memory device, the sleep transistor is turned off, which helps in minimizing leakage current between supply rails. During the sleep mode, a portion of the memory device remains powered on. During a wake up event (also referred to as wake up mode), when the chip transitions from sleep mode to an active mode, a large in-rush current could result from internal nodes transitioning through non-rail voltages. Such a situation is a disadvantage of conventional sleep transistor controlled power management circuits.
Referring to FIG. 1, a conventional power management circuit 100 for an Integrated Circuit (IC)/memory device is illustrated. The power management circuit 100 comprises a plurality of N-channel Metal Oxide Semiconductor (NMOS) transistors configured as sleep mode transistors 110. Control inputs of the sleep mode transistors 110 are connected in a daisy chain configuration (i.e., the control input of each sleep mode transistor 110 is coupled in series with the control input of a previous sleep mode transistor 110). A delay unit 120 is coupled between each pair of sleep mode transistors 110 (i.e., coupled to the control input of each transistor) to enable a staggered turn-on of the sleep mode transistors 110. A control signal wake up is applied to a control terminal of a first transistor 110 of the plurality of sleep mode transistors 110. The power management circuit 100 is coupled to a global ground supply vgnd and a local ground supply vgnd_virt.
Referring to FIG. 2, a waveform 200 illustrates a transition from a sleep event to a wake up event in a conventional memory device. In a first step, during a wake up event, a sleep signal transitions from logic 0 to logic 1. In a second step, an in-rush current Irush is generated, because internal nodes of the memory device transition through non-supply rail voltages. Both the first and second steps refer to operational modes of the power management circuit 100.
A disadvantage of the conventional power management circuit 100 is that the daisy chaining of the control inputs requires a single control signal wakeup to traverse large areas of the memory device. Such a situation further requires buffering (i.e., coupling of delay units with transistors) that leads to large leakage current through the buffers (i.e., dynamic in-rush current). Thus, timing becomes complicated in terms of determining when the daisy chain gets completely powered on and off. Moreover, the conventional power management circuit 100 consumes more area.
It is therefore desirable to provide a power management circuit that controls in-rush current during transition from sleep mode to wake up mode of the memory device. The power management circuit should further prevent any disturbance in the memory data.